old; use kgcc64

10 files changed, 0 insertions, 2002 deletions

diff --git a/sys-devel/gcc-mips64/ChangeLog b/sys-devel/gcc-mips64/ChangeLog
deleted file mode 100644
index 7281a969180d..000000000000
--- a/sys-devel/gcc-mips64/ChangeLog
+++ /dev/null
@@ -1,111 +0,0 @@
-# ChangeLog for sys-devel/gcc-mips64
-# Copyright 2000-2006 Gentoo Foundation; Distributed under the GPL v2
-# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc-mips64/ChangeLog,v 1.21 2006/08/17 16:08:47 kumba Exp $
-
-  17 Aug 2006; Joshua Kinard <kumba@gentoo.org> -gcc-mips64-3.4.4.ebuild,
-  -gcc-mips64-3.4.5.ebuild, gcc-mips64-3.4.6.ebuild:
-  Remove older ebuilds and make kgcc64 a blocker for gcc-mips64.
-
-  12 Jun 2006; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.4.6.ebuild:
-  Marked stable on mips -- we want it for release building.
-
-  06 Jun 2006; Jeremy Huddleston <eradicator@gentoo.org>
-  gcc-mips64-3.4.4.ebuild, gcc-mips64-3.4.5.ebuild, gcc-mips64-3.4.6.ebuild:
-  Updated DEPEND to accept eselect-compiler.
-
-*gcc-mips64-3.4.6 (30 May 2006)
-
-  30 May 2006; Joshua Kinard <kumba@gentoo.org>
-  +files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch,
-  gcc-mips64-3.4.5.ebuild, +gcc-mips64-3.4.6.ebuild:
-  Bump to 3.4.6, and mark 3.4.5 as stable.
-
-  28 Dec 2005; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.4.4.ebuild,
-  gcc-mips64-3.4.5.ebuild:
-  Remove unused local var
-
-  28 Dec 2005; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.4.4.ebuild,
-  gcc-mips64-3.4.5.ebuild:
-  Minor ebuild cleanups
-
-*gcc-mips64-3.4.5 (25 Dec 2005)
-
-  25 Dec 2005; Joshua Kinard <kumba@gentoo.org> -gcc-mips64-3.4.3-r1.ebuild,
-  gcc-mips64-3.4.4.ebuild, +gcc-mips64-3.4.5.ebuild:
-  Import 3.4.5 for gcc-mips64; remove 3.4.3-r1 and mark 3.4.4 as stable. This
-  will probably be the last release of gcc-mips64. sys-devel/kgcc64 will
-  deprecate this and other arch-specific kernel compilers.
-
-  25 Dec 2005; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.4.4.ebuild:
-  Allow gcc-mips64 to detect whether it's in a glibc or uclibc userland, and
-  modify its CHOST accordingly.
-
-*gcc-mips64-3.4.4 (16 Oct 2005)
-
-  16 Oct 2005; Joshua Kinard <kumba@gentoo.org>
-  +files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch,
-  +files/gcc-3.4.x-mips-add-march-r10k.patch, -gcc-mips64-3.3.4.ebuild,
-  +gcc-mips64-3.4.4.ebuild:
-  Import a gcc-3.4.4 kernel compiler for mips64.
-
-  06 Feb 2005; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.4.3-r1.ebuild:
-  Marked stable on mips.
-
-*gcc-mips64-3.4.3-r1 (09 Jan 2005)
-
-  09 Jan 2005; Joshua Kinard <kumba@gentoo.org>
-  +files/gcc-3.4.2-mips-ip28_cache_barriers.patch,
-  +gcc-mips64-3.4.3-r1.ebuild, -gcc-mips64-3.4.3.ebuild:
-  Add ip28 cache barrier patch for gcc-mips64. Anyone using this probably has an
-  inkling of what it does. Only used in this case for kernels. The system gcc
-  can use it for other things is absolutely needed.
-
-  09 Dec 2004; Joshua Kinard <kumba@gentoo.org>
-  -files/gcc-3.3.1-gentoo-branding.patch,
-  -files/gcc-3.3.2-gentoo-branding.patch,
-  -files/gcc-3.3.3-gentoo-branding.patch, -gcc-mips64-3.3.1.ebuild,
-  -gcc-mips64-3.3.2.ebuild, -gcc-mips64-3.3.3.ebuild, gcc-mips64-3.3.4.ebuild,
-  gcc-mips64-3.4.3.ebuild:
-  Fix message in postinst to give correct commands for 2.4.x and 2.6.x builds,
-  and remove old versions.
-
-*gcc-mips64-3.4.3 (11 Nov 2004)
-
-  11 Nov 2004; Joshua Kinard <kumba@gentoo.org> +gcc-mips64-3.4.3.ebuild:
-  Added ebuild for gcc-mips64-3.4.3.
-
-  06 Sep 2004; Ciaran McCreesh <ciaranm@gentoo.org> gcc-mips64-3.3.1.ebuild,
-  gcc-mips64-3.3.2.ebuild, gcc-mips64-3.3.3.ebuild, gcc-mips64-3.3.4.ebuild:
-  Switch to use epause and ebeep, bug #62950
-
-*gcc-mips64-3.3.4 (22 Jul 2004)
-
-  22 Jul 2004; Joshua Kinard <kumba@gentoo.org>
-  +files/gcc-3.3.4-gentoo-branding.patch, +gcc-mips64-3.3.4.ebuild:
-  Added ebuild for 3.3.4 version of mips64 compiler.
-
-  02 Jul 2004; Jeremy Huddleston <eradicator@gentoo.org>
-  gcc-mips64-3.3.1.ebuild, gcc-mips64-3.3.2.ebuild, gcc-mips64-3.3.3.ebuild:
-  virtual/glibc -> virtual/libc
-
-  27 Apr 2004; Aron Griffis <agriffis@gentoo.org> gcc-mips64-3.3.1.ebuild,
-  gcc-mips64-3.3.2.ebuild:
-  Add inherit eutils
-
-*gcc-mips64-3.3.3 (18 Feb 2004)
-
-  18 Feb 2004; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.3.1.ebuild,
-  gcc-mips64-3.3.2.ebuild, gcc-mips64-3.3.3.ebuild,
-  files/gcc-3.3.3-gentoo-branding.patch:
-  New gcc-3.3.3 release (on 20040214) and also includes a 20040217 branch update
-  to match the system compiler.
-
-*gcc-mips64-3.3.2 (16 Nov 2003)
-*gcc-mips64-3.3.1 (16 Nov 2003)
-
-  16 Nov 2003; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.3.1.ebuild,
-  gcc-mips64-3.3.2.ebuild, files/gcc-3.3.1-gentoo-branding.patch,
-  files/gcc-3.3.2-gentoo-branding.patch:
-  Initial revisions of minimal ebuilds which builds a kernel compiler for mips64
-  kernels
-
diff --git a/sys-devel/gcc-mips64/Manifest b/sys-devel/gcc-mips64/Manifest
deleted file mode 100644
index 560d99737182..000000000000
--- a/sys-devel/gcc-mips64/Manifest
+++ /dev/null
@@ -1,36 +0,0 @@
-AUX gcc-3.3.4-gentoo-branding.patch 874 RMD160 6fb3fb88248b9ee25f7eb1f5fea6303b723afbc6 SHA1 a0e1d7f867fa281fff061bf055c0b6d4dcef2ba1 SHA256 aa4c37bf45c1b67ac0f24fed850dca130933351f9ed35672599b6fcb96cfd0a3
-MD5 e411938ca2908079a2359fed5cb3b442 files/gcc-3.3.4-gentoo-branding.patch 874
-RMD160 6fb3fb88248b9ee25f7eb1f5fea6303b723afbc6 files/gcc-3.3.4-gentoo-branding.patch 874
-SHA256 aa4c37bf45c1b67ac0f24fed850dca130933351f9ed35672599b6fcb96cfd0a3 files/gcc-3.3.4-gentoo-branding.patch 874
-AUX gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118 RMD160 4fdcab01f80301f39b7c088750f180d95f03384e SHA1 d5c090642444b300980301526245140717893e8d SHA256 65261236a04002d6db44d4522f1dd0ebc34dc8f17244feed535230900c235fe5
-MD5 1134e9dabbd6dfba1d91015851f02a2b files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118
-RMD160 4fdcab01f80301f39b7c088750f180d95f03384e files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118
-SHA256 65261236a04002d6db44d4522f1dd0ebc34dc8f17244feed535230900c235fe5 files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118
-AUX gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951 RMD160 fa7caaf9b41ed22ed5ccb1649c693248895ec3fb SHA1 cc60d62597865fef56844bc3e92640f2c64a98db SHA256 8cef3779bc962b9a9c20daabea28791514b6f54824659e2f5824c493cdc3f6c7
-MD5 d49acaf7a8dc1f939f4d05cee97ac3a5 files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951
-RMD160 fa7caaf9b41ed22ed5ccb1649c693248895ec3fb files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951
-SHA256 8cef3779bc962b9a9c20daabea28791514b6f54824659e2f5824c493cdc3f6c7 files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951
-AUX gcc-3.4.2-mips-ip28_cache_barriers.patch 12545 RMD160 fe86ed49435828cdcfe0692aa4a8816d684268af SHA1 a87d993d01416a399e30f5143c1e5455979e8b67 SHA256 e88a5539732816deccaa195f48ee1fd719de82a91866cfe3ec0ca9474daafb4e
-MD5 f3a1b668077c6486c542dcef1cdd9672 files/gcc-3.4.2-mips-ip28_cache_barriers.patch 12545
-RMD160 fe86ed49435828cdcfe0692aa4a8816d684268af files/gcc-3.4.2-mips-ip28_cache_barriers.patch 12545
-SHA256 e88a5539732816deccaa195f48ee1fd719de82a91866cfe3ec0ca9474daafb4e files/gcc-3.4.2-mips-ip28_cache_barriers.patch 12545
-AUX gcc-3.4.x-mips-add-march-r10k.patch 14248 RMD160 25f72003b241836ec3e08ae4108a39b0ffd9b170 SHA1 abc47bce08334eafc65d167cfdbaaa0c68663248 SHA256 10d6947954f03145d8ac16f497826cf25583d37f0e1e63b9df1a33d91f59e2c8
-MD5 b2922cfe76692e7d2b373a0a255f405e files/gcc-3.4.x-mips-add-march-r10k.patch 14248
-RMD160 25f72003b241836ec3e08ae4108a39b0ffd9b170 files/gcc-3.4.x-mips-add-march-r10k.patch 14248
-SHA256 10d6947954f03145d8ac16f497826cf25583d37f0e1e63b9df1a33d91f59e2c8 files/gcc-3.4.x-mips-add-march-r10k.patch 14248
-DIST gcc-3.4.6.tar.bz2 28193401 RMD160 b15003368cedc7964f6ceaee0c39ddc43a46c442 SHA1 97b290fdc572c8e490b3b39f243e69bacad23c2b SHA256 7791a601878b765669022b8b3409fba33cc72f9e39340fec8af6d0e6f72dec39
-EBUILD gcc-mips64-3.4.6.ebuild 3936 RMD160 fe2bb04f7ba19076df20351f60639ebca67d995f SHA1 a16cd686feb40210934c68aed55eec2351d2ef1b SHA256 14c3eea7a8f4c443d579ddeaa4396d20a90fe5a8515a9265c40b0bb95c61a238
-MD5 01d1cf154b24079b408096be7741cb4d gcc-mips64-3.4.6.ebuild 3936
-RMD160 fe2bb04f7ba19076df20351f60639ebca67d995f gcc-mips64-3.4.6.ebuild 3936
-SHA256 14c3eea7a8f4c443d579ddeaa4396d20a90fe5a8515a9265c40b0bb95c61a238 gcc-mips64-3.4.6.ebuild 3936
-MISC ChangeLog 4454 RMD160 cf46bbca04b3c83360b923e8069511fda888750c SHA1 e568eb015b7c38d7a06fe2127bd0794a5735f0d9 SHA256 21e037d57caeda419cee42257be3545fd57b0767087d97c8fd93a90d00bc5624
-MD5 33f1756ec0d804af3d9d121bc6635b7d ChangeLog 4454
-RMD160 cf46bbca04b3c83360b923e8069511fda888750c ChangeLog 4454
-SHA256 21e037d57caeda419cee42257be3545fd57b0767087d97c8fd93a90d00bc5624 ChangeLog 4454
-MISC metadata.xml 364 RMD160 dcd8036943975744729bdacd32830685312e2859 SHA1 d6dfbbe9a53e6b572cee01e3b916e156bb8c06e4 SHA256 389476a4f82ae4c3279e1c36e7db17a470c54b84507a942ee5b99096e7083d04
-MD5 efda60760635b5f29e31a8f730a73086 metadata.xml 364
-RMD160 dcd8036943975744729bdacd32830685312e2859 metadata.xml 364
-SHA256 389476a4f82ae4c3279e1c36e7db17a470c54b84507a942ee5b99096e7083d04 metadata.xml 364
-MD5 8fc27b2f831bbe81d5f3bc7005a44ca0 files/digest-gcc-mips64-3.4.6 238
-RMD160 e740aa34a8ebbb3a6b339afb74c9b7ad4dab824f files/digest-gcc-mips64-3.4.6 238
-SHA256 977bbf6314223f25cab3dcdb74a586dbadf8f3aa6218d570483f8b684a27e764 files/digest-gcc-mips64-3.4.6 238
diff --git a/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.6 b/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.6
deleted file mode 100644
index b439e21c4406..000000000000
--- a/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.6
+++ /dev/null
@@ -1,3 +0,0 @@
-MD5 4a21ac777d4b5617283ce488b808da7b gcc-3.4.6.tar.bz2 28193401
-RMD160 b15003368cedc7964f6ceaee0c39ddc43a46c442 gcc-3.4.6.tar.bz2 28193401
-SHA256 7791a601878b765669022b8b3409fba33cc72f9e39340fec8af6d0e6f72dec39 gcc-3.4.6.tar.bz2 28193401
diff --git a/sys-devel/gcc-mips64/files/gcc-3.3.4-gentoo-branding.patch b/sys-devel/gcc-mips64/files/gcc-3.3.4-gentoo-branding.patch
deleted file mode 100644
index e2caf9b0218b..000000000000
--- a/sys-devel/gcc-mips64/files/gcc-3.3.4-gentoo-branding.patch
+++ /dev/null
@@ -1,18 +0,0 @@
-diff -Naurp gcc-3.3.orig/gcc/version.c gcc-3.3/gcc/version.c
---- gcc-3.3.orig/gcc/version.c	2003-05-13 17:26:03.000000000 -0400
-+++ gcc-3.3/gcc/version.c	2003-05-16 14:35:08.000000000 -0400
-@@ -6,7 +6,7 @@
-    please modify this string to indicate that, e.g. by putting your
-    organization's name in parentheses at the end of the string.  */
- 
--const char version_string[] = "3.3.4";
-+const char version_string[] = "3.3.4 @GENTOO@";
- 
- /* This is the location of the online document giving instructions for
-    reporting bugs.  If you distribute a modified version of GCC,
-@@ -15,4 +15,4 @@ const char version_string[] = "3.3";
-    forward us bugs reported to you, if you determine that they are
-    not bugs in your modifications.)  */
- 
--const char bug_report_url[] = "<URL:http://gcc.gnu.org/bugs.html>";
-+const char bug_report_url[] = "<URL:http://bugs.gentoo.org/>";
diff --git a/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch b/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch
deleted file mode 100644
index d91c9f2738d5..000000000000
--- a/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch
+++ /dev/null
@@ -1,458 +0,0 @@
---- gcc-3.4.2/gcc/config/mips/mips.h	Thu Jul 15 02:42:47 2004
-+++ gcc-3.4.2/gcc/config/mips/mips.h	Sat Sep 18 00:41:48 2004
-@@ -122,6 +122,7 @@
- extern const char *mips_isa_string;	/* for -mips{1,2,3,4} */
- extern const char *mips_abi_string;	/* for -mabi={32,n32,64} */
- extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
-+extern const char *mips_ip28_cache_barrier;/* for -mip28-cache-barrier */
- extern int mips_string_length;		/* length of strings for mips16 */
- extern const struct mips_cpu_info mips_cpu_info_table[];
- extern const struct mips_cpu_info *mips_arch_info;
-@@ -333,6 +334,7 @@
- #define TARGET_MIPS9000             (mips_arch == PROCESSOR_R9000)
- #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1)
- #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
-+#define TARGET_IP28                 (mips_ip28_cache_barrier != 0)
- 
- /* Scheduling target defines.  */
- #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
-@@ -752,6 +754,8 @@
-       N_("Don't call any cache flush functions"), 0},			\
-   { "flush-func=", &mips_cache_flush_func,				\
-       N_("Specify cache flush function"), 0},				\
-+  { "ip28-cache-barrier", &mips_ip28_cache_barrier,			\
-+      N_("Generate special cache barriers for SGI Indigo2 R10k"), 0},	\
- }
- 
- /* This is meant to be redefined in the host dependent files.  */
-@@ -3448,3 +3452,11 @@
- 	" TEXT_SECTION_ASM_OP);
- #endif
- #endif
-+
-+#define ASM_OUTPUT_R10K_CACHE_BARRIER(STREAM)		\
-+  fprintf (STREAM, "\tcache 0x14,0($sp)\t%s Cache Barrier\n", ASM_COMMENT_START)
-+
-+/*
-+ * mips.h	Thu Jul 15 02:42:47 2004
-+ * mips.h	Fri Sep 17 23:18:19 2004	ip28
-+ */
---- gcc-3.4.2/gcc/config/mips/mips.c	Wed Jul  7 21:21:10 2004
-+++ gcc-3.4.2/gcc/config/mips/mips.c	Fri Sep 17 23:33:44 2004
-@@ -502,6 +502,11 @@
- 
- const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
- 
-+/* Nonzero means generate special cache barriers to inhibit speculative
-+   stores which might endanger cache coherency or reference invalid
-+   addresses (especially on SGI's Indigo2 R10k (IP28)).  */
-+const char *mips_ip28_cache_barrier;
-+
- /* If TRUE, we split addresses into their high and low parts in the RTL.  */
- int mips_split_addresses;
- 
-@@ -9676,3 +9681,7 @@
- #endif /* TARGET_IRIX */
- 
- #include "gt-mips.h"
-+/*
-+ * mips.c	Wed Jul  7 21:21:10 2004
-+ * mips.c	Fri Sep 17 23:25:53 2004	ip28
-+ */
---- gcc-3.4.2/gcc/final.c	Sun Jan 18 23:39:57 2004
-+++ gcc-3.4.2/gcc/final.c	Thu Apr  7 00:00:05 2005
-@@ -146,6 +146,13 @@
- 
- static rtx last_ignored_compare = 0;
- 
-+/* Flag indicating this insn is the start of a new basic block.  */
-+
-+#define NEW_BLOCK_LABEL  1
-+#define NEW_BLOCK_BRANCH 2
-+
-+static int new_block = NEW_BLOCK_LABEL;
-+
- /* Assign a unique number to each insn that is output.
-    This can be used to generate unique local labels.  */
- 
-@@ -235,6 +242,7 @@
- #ifdef HAVE_ATTR_length
- static int align_fuzz (rtx, rtx, int, unsigned);
- #endif
-+static int output_store_cache_barrier (FILE *, rtx);
- 
- /* Initialize data in final at the beginning of a compilation.  */
- 
-@@ -1505,6 +1513,7 @@
-   int seen = 0;
- 
-   last_ignored_compare = 0;
-+  new_block = NEW_BLOCK_LABEL;
- 
- #ifdef SDB_DEBUGGING_INFO
-   /* When producing SDB debugging info, delete troublesome line number
-@@ -1571,6 +1580,7 @@
- 
-       insn = final_scan_insn (insn, file, optimize, prescan, 0, &seen);
-     }
-+  new_block = 0;
- }
- 
- const char *
-@@ -1851,6 +1861,7 @@
- #endif
-       if (prescan > 0)
- 	break;
-+      new_block = NEW_BLOCK_LABEL;
- 
-       if (LABEL_NAME (insn))
- 	(*debug_hooks->label) (insn);
-@@ -2009,6 +2020,26 @@
- 
- 	    break;
- 	  }
-+
-+#ifdef TARGET_IP28
-+	if (new_block)
-+	  {
-+	    /* .reorder: not really in the branch-delay-slot. */
-+	    if (! set_noreorder)
-+	      new_block = NEW_BLOCK_LABEL;
-+
-+	    if (new_block == NEW_BLOCK_BRANCH)
-+	      /* Not yet, only *after* the branch-delay-slot ! */
-+	      new_block = NEW_BLOCK_LABEL;
-+	    else
-+	      {
-+	        if (TARGET_IP28)
-+	          output_store_cache_barrier (file, insn);
-+	        new_block = 0;
-+	      }
-+	  }
-+#endif
-+
- 	/* Output this line note if it is the first or the last line
- 	   note in a row.  */
- 	if (notice_source_line (insn))
-@@ -2132,8 +2163,29 @@
- 	       clobbered by the function.  */
- 	    if (GET_CODE (XVECEXP (body, 0, 0)) == CALL_INSN)
- 	      {
-+#ifdef TARGET_IP28
-+	        if (TARGET_IP28)
-+	          new_block = NEW_BLOCK_LABEL;
-+#endif
- 		CC_STATUS_INIT;
- 	      }
-+#ifdef TARGET_IP28
-+	    /* Following a conditional branch sequence, we have a new basic
-+	       block.  */
-+	    if (TARGET_IP28)
-+	      {
-+		rtx insn = XVECEXP (body, 0, 0);
-+		rtx body = PATTERN (insn);
-+
-+		if ((GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == SET
-+		     && GET_CODE (SET_SRC (body)) != LABEL_REF)
-+		    || (GET_CODE (insn) == JUMP_INSN
-+			&& GET_CODE (body) == PARALLEL
-+			&& GET_CODE (XVECEXP (body, 0, 0)) == SET
-+			&& GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF))
-+		  new_block = NEW_BLOCK_LABEL;
-+	      }
-+#endif
- 	    break;
- 	  }
- 
-@@ -2188,6 +2240,20 @@
- 	  }
- #endif
- 
-+#ifdef TARGET_IP28
-+	/* Following a conditional branch, we have a new basic block.
-+	   But if we are inside a sequence, the new block starts after the
-+	   last insn of the sequence.  */
-+	if (TARGET_IP28 && final_sequence == 0
-+	    && (GET_CODE (insn) == CALL_INSN
-+	        || (GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == SET
-+	            && GET_CODE (SET_SRC (body)) != LABEL_REF)
-+	        || (GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == PARALLEL
-+	            && GET_CODE (XVECEXP (body, 0, 0)) == SET
-+	            && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF)))
-+	      new_block = NEW_BLOCK_BRANCH;
-+#endif
-+
- #ifndef STACK_REGS
- 	/* Don't bother outputting obvious no-ops, even without -O.
- 	   This optimization is fast and doesn't interfere with debugging.
-@@ -2402,6 +2468,7 @@
- 
- 	    if (prev_nonnote_insn (insn) != last_ignored_compare)
- 	      abort ();
-+	    new_block = 0;
- 
- 	    /* We have already processed the notes between the setter and
- 	       the user.  Make sure we don't process them again, this is
-@@ -2435,6 +2502,7 @@
- 	    abort ();
- #endif
- 
-+	    new_block = 0;
- 	    return new;
- 	  }
- 
-@@ -3866,3 +3934,254 @@
-       symbol_queue_size = 0;
-     }
- }
-+
-+
-+#ifdef TARGET_IP28
-+
-+/* Check, whether an instruction is a possibly harmful store instruction,
-+   i.e. a store which might cause damage, if speculatively executed. */
-+
-+static rtx
-+find_mem_expr (rtx xexp)
-+{
-+  if (xexp)
-+    {
-+      const char *fmt;
-+      int i, j, lng;
-+      rtx x;
-+      RTX_CODE code = GET_CODE (xexp);
-+
-+      if (MEM == code)
-+        return xexp;
-+
-+      fmt = GET_RTX_FORMAT (code);
-+      lng = GET_RTX_LENGTH (code);
-+
-+      for (i = 0; i < lng; ++i)
-+        switch (fmt[i])
-+          {
-+          case 'e':
-+            x = find_mem_expr (XEXP (xexp, i));
-+            if (x)
-+              return x;
-+            break;
-+          case 'E':
-+            if (XVEC (xexp, i))
-+              for (j = 0; j < XVECLEN (xexp, i); ++j)
-+                {
-+                  x = find_mem_expr (XVECEXP (xexp, i, j));
-+                  if (x)
-+                    return x;
-+                }
-+          }
-+    }
-+  return 0;
-+}
-+
-+static int
-+check_mem_expr (rtx memx)
-+{
-+  /* Check the expression `memx' (with type GET_CODE(memx) == MEM)
-+     for the most common stackpointer-addressing modes.
-+     It's not worthwile to avoid a cache barrier also on the
-+     remaining unfrequently used modes.  */
-+  rtx x = XEXP (memx, 0);
-+  switch (GET_CODE (x))
-+    {
-+    case REG:
-+      if (REGNO (x) == STACK_POINTER_REGNUM)
-+        return 0;
-+    default:
-+      break;
-+    case PLUS: case MINUS: /* always `SP + const' ? */
-+      if (GET_CODE (XEXP (x, 1)) == REG
-+          && REGNO (XEXP (x, 1)) == STACK_POINTER_REGNUM)
-+        return 0;
-+    case NEG: case SIGN_EXTEND: case ZERO_EXTEND:
-+      if (GET_CODE (XEXP (x, 0)) == REG
-+          && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM)
-+        return 0;
-+    }
-+
-+  /* Stores/Loads to/from constant addresses can be considered
-+     harmless, since:
-+     1)  the address is always valid, even when taken speculatively.
-+     2a) the location is (hopefully) never used as a dma-target, thus
-+         there is no danger of cache-inconsistency.
-+     2b) uncached loads/stores are guaranteed to be non-speculative. */
-+  if ( CONSTANT_P(x) )
-+    return 0;
-+
-+  return 1;
-+}
-+
-+/* inline */ static int
-+check_pattern_for_store (rtx body)
-+{
-+  /* Check for (set (mem:M (non_stackpointer_address) ...)).  Here we
-+     assume, that addressing with the stackpointer accesses neither
-+     uncached-aliased nor invalid memory.  (May be, this applies to the
-+     global pointer and frame pointer also, but its saver not to assume
-+     it. And probably it's not worthwile to regard these registers)
-+
-+     Speculative loads from invalid addresses also cause bus errors...
-+     So check for (set (reg:M ...) (mem:M (non_stackpointer_address)))
-+     too. */
-+
-+  if (body && GET_CODE (body) == SET)
-+    {
-+      rtx x = find_mem_expr (body);
-+
-+      if (x && check_mem_expr (x))
-+        return 1;
-+    }
-+  return 0;
-+}
-+
-+static int
-+check_insn_for_store (int state, rtx insn)
-+{
-+  /* Check for (ins (set (mem:M (dangerous_address)) ...)) or end of the
-+     current basic block.
-+     Criteria to recognize end-of/next basic-block are reduplicated here
-+     from final_scan_insn. */
-+
-+  rtx body;
-+  int code;
-+
-+  if (INSN_DELETED_P (insn))
-+    return 0;
-+
-+  switch (code = GET_CODE (insn))
-+    {
-+    case CODE_LABEL:
-+      return -1;
-+    case CALL_INSN:
-+    case JUMP_INSN:
-+    case INSN:
-+      body = PATTERN (insn);
-+      if (GET_CODE (body) == SEQUENCE)
-+        {
-+          /* A delayed-branch sequence */
-+          rtx ins0 = XVECEXP (body, 0, 0);
-+          rtx pat0 = PATTERN (ins0);
-+          int i;
-+          for (i = 0; i < XVECLEN (body, 0); i++)
-+            {
-+              rtx insq = XVECEXP (body, 0, i);
-+              if (! INSN_DELETED_P (insq))
-+                {
-+                  int j = check_insn_for_store (state|1, insq);
-+                  if (j)
-+                    return j;
-+                }
-+            }
-+          /* Following a conditional branch sequence, we have a new
-+             basic block.  */
-+          if (GET_CODE (ins0) == JUMP_INSN)
-+            if ((GET_CODE (pat0) == SET
-+                 && GET_CODE (SET_SRC (pat0)) != LABEL_REF)
-+                || (GET_CODE (pat0) == PARALLEL
-+                    && GET_CODE (XVECEXP (pat0, 0, 0)) == SET
-+                    && GET_CODE (SET_SRC (XVECEXP (pat0, 0, 0))) != LABEL_REF))
-+              return -1;
-+          /* Handle a call sequence like a conditional branch sequence */
-+          if (GET_CODE (ins0) == CALL_INSN)
-+            return -1;
-+          break;
-+        }
-+      if (GET_CODE (body) == PARALLEL)
-+        {
-+          int i;
-+          for (i = 0; i < XVECLEN (body, 0); i++)
-+            if (check_pattern_for_store (XVECEXP (body, 0, i)))
-+              return 1;
-+        }
-+      /* Now, only a `simple' INSN or JUMP_INSN remains to be checked. */
-+      if (code == INSN)
-+        {
-+          /* Since we don't know, what's inside, we must take inline
-+             assembly to be dangerous */
-+          if (GET_CODE (body) == ASM_INPUT)
-+            return 1;
-+
-+          if (check_pattern_for_store (body))
-+            return 1;
-+        }
-+      /* Handle a CALL_INSN instruction like a conditional branch */
-+      if (code == JUMP_INSN || code == CALL_INSN)
-+        {
-+          /* Following a conditional branch, we have a new basic block. */
-+          int ckds = 0;
-+          if (code == CALL_INSN)
-+            ckds = 1;
-+          else
-+            {
-+              code = GET_CODE (body);
-+              if ((code == SET
-+                   && GET_CODE (SET_SRC (body)) != LABEL_REF)
-+                  || (code == PARALLEL
-+                      && GET_CODE (XVECEXP (body, 0, 0)) == SET
-+                      && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF))
-+                ckds = 1;
-+            }
-+          if (ckds)
-+            {
-+              /* But check insn(s) in delay-slot first.  If we could know in
-+                 advance that this jump is in `.reorder' mode, where gas will
-+                 insert a `nop' into the delay-slot, we could skip this test.
-+                 Since we don't know, always assume `.noreorder', sometimes
-+                 emitting a cache-barrier, that isn't needed.  */
-+              /* But if we are here recursively, already checking a (pseudo-)
-+                 delay-slot, we are done.  */
-+              if ( !(state & 2) )
-+                for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
-+                  switch (GET_CODE (insn))
-+                    {
-+                    case INSN:
-+                      if (check_insn_for_store (state|1|2, insn) > 0)
-+                        return 1;
-+                    case CODE_LABEL:
-+                    case CALL_INSN:
-+                    case JUMP_INSN:
-+                      return -1;
-+                    default:
-+                      /* skip NOTE,... */;
-+                    }
-+              return -1;
-+            }
-+        }
-+      /*break*/
-+    }
-+  return 0;
-+}
-+
-+/* Scan a basic block, starting with `insn', for a possibly harmful store
-+   instruction.  If found, output a cache barrier at the start of this
-+   block.  */
-+
-+static int
-+output_store_cache_barrier (FILE *file, rtx insn)
-+{
-+  for (; insn; insn = NEXT_INSN (insn))
-+    {
-+      int found = check_insn_for_store (0, insn);
-+      if (found < 0)
-+        break;
-+      if (found > 0)
-+        {
-+          /* found critical store instruction */
-+          ASM_OUTPUT_R10K_CACHE_BARRIER(file);
-+          return 1;
-+        }
-+    }
-+  fprintf(file, "\t%s Cache Barrier omitted.\n", ASM_COMMENT_START);
-+  return 0;
-+}
-+
-+#endif /* TARGET_IP28 */
-+
-+/*
-+ * final.c	Sun Jan 18 23:39:57 2004
-+ * final.c	Sat Sep 18 00:23:34 2004	ip28
-+ */
diff --git a/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch b/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch
deleted file mode 100644
index 02edc3709e2a..000000000000
--- a/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch
+++ /dev/null
@@ -1,366 +0,0 @@
-diff -Naurp gcc-3.4.6.orig/gcc/config/mips/mips.c gcc-3.4.6/gcc/config/mips/mips.c
---- gcc-3.4.6.orig/gcc/config/mips/mips.c	2005-07-31 04:35:15.000000000 -0400
-+++ gcc-3.4.6/gcc/config/mips/mips.c	2006-04-08 17:41:44.000000000 -0400
-@@ -8801,6 +8801,11 @@ mips_reorg (void)
- 	dbr_schedule (get_insns (), rtl_dump_file);
-       mips_avoid_hazards ();
-     }
-+  if (mips_r10k_cache_barrier)
-+    {
-+      static int r10k_insert_cache_barriers (void);
-+      r10k_insert_cache_barriers ();
-+    }
- }
- 
- /* We need to use a special set of functions to handle hard floating
-@@ -9661,5 +9666,5 @@ irix_section_type_flags (tree decl, cons
- }
- 
- #endif /* TARGET_IRIX */
--
-+#include "r10k-cacheb.c"
- #include "gt-mips.h"
-diff -Naurp gcc-3.4.6.orig/gcc/config/mips/mips.h gcc-3.4.6/gcc/config/mips/mips.h
---- gcc-3.4.6.orig/gcc/config/mips/mips.h	2004-07-14 20:42:49.000000000 -0400
-+++ gcc-3.4.6/gcc/config/mips/mips.h	2006-04-08 17:41:01.000000000 -0400
-@@ -122,6 +122,7 @@ extern const char *mips_tune_string;    
- extern const char *mips_isa_string;	/* for -mips{1,2,3,4} */
- extern const char *mips_abi_string;	/* for -mabi={32,n32,64} */
- extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
-+extern const char *mips_r10k_cache_barrier;/* for -mr10k-cache-barrier[={1,2}] */
- extern int mips_string_length;		/* length of strings for mips16 */
- extern const struct mips_cpu_info mips_cpu_info_table[];
- extern const struct mips_cpu_info *mips_arch_info;
-@@ -752,6 +753,10 @@ extern const struct mips_cpu_info *mips_
-       N_("Don't call any cache flush functions"), 0},			\
-   { "flush-func=", &mips_cache_flush_func,				\
-       N_("Specify cache flush function"), 0},				\
-+  { "r10k-cache-barrier", &mips_r10k_cache_barrier,			\
-+      N_("[=1|2]\tGenerate cache barriers for SGI Indigo2/O2 R10k"), 0},	\
-+  { "ip28-cache-barrier", &mips_r10k_cache_barrier,			\
-+      N_(""), 0},	\
- }
- 
- /* This is meant to be redefined in the host dependent files.  */
-diff -Naurp gcc-3.4.6.orig/gcc/config/mips/r10k-cacheb.c gcc-3.4.6/gcc/config/mips/r10k-cacheb.c
---- gcc-3.4.6.orig/gcc/config/mips/r10k-cacheb.c	1969-12-31 19:00:00.000000000 -0500
-+++ gcc-3.4.6/gcc/config/mips/r10k-cacheb.c	2006-04-08 17:41:22.000000000 -0400
-@@ -0,0 +1,318 @@
-+/* Subroutines used for MIPS code generation: generate cache-barriers
-+   for SiliconGraphics IP28 and IP32/R10000 kernel-code.
-+   Copyright (C) 2005,2006 peter fuerst, pf@net.alphadv.de.
-+
-+This file is intended to become part of GCC.
-+
-+This file is free software; you can redistribute it and/or modify it
-+under the terms of the GNU General Public License as published
-+by the Free Software Foundation; either version 2, or (at your
-+option) any later version.
-+
-+This file is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING.  If not, write to the
-+Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
-+MA  02110-1301  USA.  */
-+
-+
-+#define ASM_R10K_CACHE_BARRIER	"cache 0x14,0($sp)"
-+
-+/* Some macros, ported back from 4.x ... */
-+
-+#define CALL_P(X)  (GET_CODE (X) == CALL_INSN)
-+#define MEM_P(X)   (GET_CODE (X) == MEM)
-+#define NONJUMP_INSN_P(X)  (GET_CODE (X) == INSN)
-+
-+#define SEQ_BEGIN(insn)                        \
-+  (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE  \
-+   ? XVECEXP (PATTERN (insn), 0, 0)                        \
-+   : (insn))
-+
-+#define SEQ_END(insn)                          \
-+  (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE      \
-+   ? XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1)  \
-+   : (insn))
-+
-+#define FOR_EACH_SUBINSN(subinsn, insn)        \
-+  for ((subinsn) = SEQ_BEGIN (insn);       \
-+       (subinsn) != NEXT_INSN (SEQ_END (insn));    \
-+       (subinsn) = NEXT_INSN (subinsn))
-+
-+
-+/* Nonzero means generate special cache barriers to inhibit speculative
-+   stores which might endanger cache coherency or reference invalid
-+   addresses (especially on SGI's Indigo2 R10k (IP28)).  */
-+const char *mips_r10k_cache_barrier;
-+static int TARGET_R10K_SPECEX;
-+
-+/* Check, whether an instruction is a possibly harmful store instruction,
-+   i.e. a store which might cause damage, if speculatively executed. */
-+
-+/* Return truth value whether the expression `*memx' instantiates
-+   (mem:M (not (stackpointer_address or constant))). */
-+
-+static int
-+is_stack_pointer (rtx *x, void *data)
-+{
-+  return (*x == stack_pointer_rtx);
-+}
-+
-+static int
-+check_p_mem_expr (rtx *memx, void *data)
-+{
-+  if (!MEM_P (*memx) || for_each_rtx (memx, is_stack_pointer, 0))
-+    return 0;
-+
-+  /* Stores/Loads to/from constant addresses can be considered
-+     harmless, since:
-+     1)  the address is always valid, even when taken speculatively.
-+     2a) the location is (hopefully) never used as a dma-target, thus
-+         there is no danger of cache-inconsistency.
-+     2b) uncached loads/stores are guaranteed to be non-speculative. */
-+  if ( CONSTANT_P(XEXP (*memx, 0)) )
-+    return 0;
-+
-+  return 1;
-+}
-+
-+/* Return truth value whether we find (set (mem:M (non_stackpointer_address)
-+   ...)) in instruction-pattern `body'.
-+   Here we assume, that addressing with the stackpointer accesses neither
-+   uncached-aliased nor invalid memory.
-+   (May be, this applies to the global pointer and frame pointer also,
-+   but its saver not to assume it. And probably it's not worthwile to
-+   regard these registers)
-+
-+   Speculative loads from invalid addresses also cause bus errors...
-+   So check for (set (reg:M ...) (mem:M (non_stackpointer_address)))
-+   too, unless there is an enhanced bus-error handler. */
-+
-+static int
-+check_p_pattern_for_store (rtx *body, void *data)
-+{
-+  if (*body && GET_CODE (*body) == SET)
-+    {
-+      /* Cache-barriers for SET_SRC may be requested as well. */
-+      if (!(TARGET_R10K_SPECEX & 2))
-+        body = &SET_DEST(*body);
-+
-+      if (for_each_rtx (body, check_p_mem_expr, 0))
-+        return 1;
-+
-+      /* Don't traverse sub-expressions again. */
-+      return -1;
-+    }
-+  return 0;
-+}
-+
-+static int
-+strmatch (const char *txt, const char *match)
-+{
-+  return !strncmp(txt, match, strlen (match));
-+}
-+
-+/* Check for (ins (set (mem:M (dangerous_address)) ...)) or end of the
-+   current basic block in instruction `insn'.
-+   `state': (internal) recursion-counter and delayslot-flag
-+   Criteria to recognize end-of/next basic-block are reduplicated here
-+   from final_scan_insn.
-+   return >0: `insn' is critical.
-+   return <0: `insn' is at end of current basic-block.
-+   return 0:  `insn' can be ignored. */
-+
-+static int
-+check_insn_for_store (int state, rtx insn)
-+{
-+  rtx body;
-+
-+  if (INSN_DELETED_P (insn))
-+    return 0;
-+
-+  if (LABEL_P (insn))
-+    return -1;
-+
-+  if (CALL_P (insn) || JUMP_P (insn) || NONJUMP_INSN_P (insn))
-+    {
-+      body = PATTERN (insn);
-+      if (GET_CODE (body) == SEQUENCE)
-+        {
-+          /* A delayed-branch sequence. */
-+          rtx insq;
-+          FOR_EACH_SUBINSN(insq, insn)
-+            if (! INSN_DELETED_P (insq))
-+              {
-+                /* |1: delay-slot completely contained in sequence. */
-+                if (check_insn_for_store (8+state|1, insq) > 0)
-+                  return 1;
-+              }
-+          /* Following a (conditional) branch sequence, we have a new
-+             basic block.  */
-+          if (JUMP_P (SEQ_BEGIN(insn)))
-+            return -1;
-+          /* Handle a call sequence like a conditional branch sequence. */
-+          if (CALL_P (SEQ_BEGIN(insn)))
-+            return -1;
-+        }
-+      if (GET_CODE (body) == PARALLEL)
-+        if (for_each_rtx (&body, check_p_pattern_for_store, 0))
-+           return 1;
-+
-+      /* Now, only a `simple' INSN or JUMP_INSN remains to be checked. */
-+      if (NONJUMP_INSN_P (insn))
-+        {
-+          /* Since we don't know what's inside, we must take inline
-+             assembly to be dangerous. */
-+          if (GET_CODE (body) == ASM_INPUT)
-+            {
-+              const char *t = XSTR (body, 0);
-+              if (t && !strmatch(t, ASM_R10K_CACHE_BARRIER))
-+                return 1;
-+            }
-+
-+          if (check_p_pattern_for_store (&body, 0) > 0)
-+            return 1;
-+        }
-+      /* Handle a CALL_INSN instruction like a conditional branch. */
-+      if (JUMP_P (insn) || CALL_P (insn))
-+        {
-+          /* Following a (conditional) branch, we have a new basic block. */
-+          /* But check insn(s) in delay-slot first.  If we could know in
-+             advance that this jump is in `.reorder' mode, where gas will
-+             insert a `nop' into the delay-slot, we could skip this test.
-+             Since we don't know, always assume `.noreorder', sometimes
-+             emitting a cache-barrier, that isn't needed.  */
-+          /* But if we are here recursively, already checking a (pseudo-)
-+             delay-slot, we are done.  */
-+          if ( !(state & 1) )
-+            for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
-+              {
-+                if (LABEL_P (insn) || CALL_P (insn) || JUMP_P (insn))
-+                  /* Not in delay-slot at all. */
-+                  break;
-+
-+                if (NONJUMP_INSN_P (insn))
-+                  {
-+                    if (GET_CODE (PATTERN (insn)) == SEQUENCE)
-+                      /* Not in delay-slot at all. */
-+                      break;
-+
-+                    if (check_insn_for_store (8+state|1, insn) > 0)
-+                      return 1;
-+                    /* We're done anyway. */
-+                    break;
-+                  }
-+                /* skip NOTE,... */;
-+              }
-+          return -1;
-+        }
-+    }
-+  return 0;
-+}
-+
-+
-+/* Scan a basic block, starting with `insn', for a possibly harmful store
-+   instruction.  If found, output a cache barrier at the start of this
-+   block.  */
-+
-+static int
-+bb_insert_store_cache_barrier (rtx head, rtx nxtb)
-+{
-+  rtx insn = head;
-+
-+  if (!insn || insn == nxtb)
-+     return 0;
-+
-+  while ((insn = NEXT_INSN (insn)) && insn != nxtb)
-+    {
-+      int found;
-+
-+      if (NOTE_INSN_BASIC_BLOCK_P(insn)) /* See scan_1_bb_for_store() */
-+        break;
-+      
-+      found = check_insn_for_store (0, insn);
-+      if (found < 0)
-+        break;
-+      if (found > 0)
-+        {
-+          /* found critical store instruction */
-+          insn = gen_rtx_ASM_INPUT (VOIDmode,
-+                                    ASM_R10K_CACHE_BARRIER "\t"
-+                                    ASM_COMMENT_START " Cache Barrier");
-+          /* Here we rely on the assumption, that an explicit delay-slot
-+             - if any - is already embedded (in a sequence) in 'head'! */
-+          insn = emit_insn_after (insn, head);
-+          return 1;
-+        }
-+    }
-+  return 0;
-+}
-+
-+
-+/* Scan one basic block for a possibly harmful store instruction.
-+   If found, insert a cache barrier at the start of this block,
-+   return number of inserted cache_barriers. */
-+
-+static int
-+scan_1_bb_for_store (rtx head, rtx end)
-+{
-+  rtx nxtb;
-+  int count;
-+
-+  /* Note: 'end' is not necessarily reached from 'head' (hidden in
-+     SEQUENCE, PARALLEL), but 'nxtb' is. */
-+  nxtb = NEXT_INSN (end);
-+
-+  /* Each basic block starts with zero or more CODE_LABEL(s), followed
-+     by one NOTE_INSN_BASIC_BLOCK.
-+     Note: bb_head may equal next_insn(bb_end) already ! */
-+  while (head && head != nxtb && LABEL_P (head))
-+    head = NEXT_INSN (head);
-+
-+  if (!head || head == nxtb)
-+    return 0;
-+
-+  /* Handle the basic block itself, at most up to next CALL_INSN. */
-+  count = bb_insert_store_cache_barrier (head, nxtb);
-+
-+  /* 1) Handle any CALL_INSN instruction like a conditional branch.
-+     2) There may be "basic blocks" in the list, which are no basic blocks
-+        at all. (containing CODE_LABELs in the body or gathering several
-+        other basic blocks (e.g. bb5 containing bb6,bb7,bb8)). */
-+
-+  while ((head = NEXT_INSN (head)) && head != nxtb)
-+    {
-+      if (INSN_DELETED_P (head))
-+        continue;
-+
-+      /* Later we'll be called again for this bb on its own. */
-+      if (NOTE_INSN_BASIC_BLOCK_P(head))
-+        break;
-+
-+      if (CALL_P (SEQ_BEGIN (head)) || LABEL_P (head))
-+        count += bb_insert_store_cache_barrier (head, nxtb);
-+    }
-+  return count;
-+}
-+
-+static int
-+r10k_insert_cache_barriers (void)
-+{
-+  if (mips_r10k_cache_barrier)
-+    {
-+      basic_block bb;
-+
-+      const char *s = mips_r10k_cache_barrier;
-+      /* Default is to protect stores (only). */
-+      TARGET_R10K_SPECEX = 1 | strtol(*s != '=' ? s:s+1, (char**)0, 0);
-+
-+      FOR_EACH_BB (bb)
-+        if (0 <= bb->index)
-+          scan_1_bb_for_store (BB_HEAD (bb), BB_END (bb));
-+    }
-+  return 0;
-+}
diff --git a/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers.patch b/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers.patch
deleted file mode 100644
index 38b183288ba9..000000000000
--- a/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers.patch
+++ /dev/null
@@ -1,392 +0,0 @@
---- gcc-3.4.2/gcc/config/mips/mips.h	Thu Jul 15 02:42:47 2004
-+++ gcc-3.4.2/gcc/config/mips/mips.h	Sat Sep 18 00:41:48 2004
-@@ -122,6 +122,7 @@
- extern const char *mips_isa_string;	/* for -mips{1,2,3,4} */
- extern const char *mips_abi_string;	/* for -mabi={32,n32,64} */
- extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
-+extern const char *mips_ip28_cache_barrier;/* for -mip28-cache-barrier */
- extern int mips_string_length;		/* length of strings for mips16 */
- extern const struct mips_cpu_info mips_cpu_info_table[];
- extern const struct mips_cpu_info *mips_arch_info;
-@@ -333,6 +334,7 @@
- #define TARGET_MIPS9000             (mips_arch == PROCESSOR_R9000)
- #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1)
- #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
-+#define TARGET_IP28                 (mips_ip28_cache_barrier != 0)
- 
- /* Scheduling target defines.  */
- #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
-@@ -752,6 +754,8 @@
-       N_("Don't call any cache flush functions"), 0},			\
-   { "flush-func=", &mips_cache_flush_func,				\
-       N_("Specify cache flush function"), 0},				\
-+  { "ip28-cache-barrier", &mips_ip28_cache_barrier,			\
-+      N_("Generate special cache barriers for SGI Indigo2 R10k"), 0},	\
- }
- 
- /* This is meant to be redefined in the host dependent files.  */
-@@ -3448,3 +3452,11 @@
- 	" TEXT_SECTION_ASM_OP);
- #endif
- #endif
-+
-+#define ASM_OUTPUT_R10K_CACHE_BARRIER(STREAM)		\
-+  fprintf (STREAM, "\tcache 0x14,0($sp)\t%s Cache Barrier\n", ASM_COMMENT_START)
-+
-+/*
-+ * mips.h	Thu Jul 15 02:42:47 2004
-+ * mips.h	Fri Sep 17 23:18:19 2004	ip28
-+ */
---- gcc-3.4.2/gcc/config/mips/mips.c	Wed Jul  7 21:21:10 2004
-+++ gcc-3.4.2/gcc/config/mips/mips.c	Fri Sep 17 23:33:44 2004
-@@ -502,6 +502,11 @@
- 
- const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
- 
-+/* Nonzero means generate special cache barriers to inhibit speculative
-+   stores which might endanger cache coherency or reference invalid
-+   addresses (especially on SGI's Indigo2 R10k (IP28)).  */
-+const char *mips_ip28_cache_barrier;
-+
- /* If TRUE, we split addresses into their high and low parts in the RTL.  */
- int mips_split_addresses;
- 
-@@ -9676,3 +9681,7 @@
- #endif /* TARGET_IRIX */
- 
- #include "gt-mips.h"
-+/*
-+ * mips.c	Wed Jul  7 21:21:10 2004
-+ * mips.c	Fri Sep 17 23:25:53 2004	ip28
-+ */
---- gcc-3.4.2/gcc/final.c	Sun Jan 18 23:39:57 2004
-+++ gcc-3.4.2/gcc/final.c	Fri Nov 19 00:40:50 2004
-@@ -146,6 +146,13 @@
- 
- static rtx last_ignored_compare = 0;
- 
-+/* Flag indicating this insn is the start of a new basic block.  */
-+
-+#define NEW_BLOCK_LABEL  1
-+#define NEW_BLOCK_BRANCH 2
-+
-+static int new_block = NEW_BLOCK_LABEL;
-+
- /* Assign a unique number to each insn that is output.
-    This can be used to generate unique local labels.  */
- 
-@@ -235,6 +242,7 @@
- #ifdef HAVE_ATTR_length
- static int align_fuzz (rtx, rtx, int, unsigned);
- #endif
-+static int output_store_cache_barrier (FILE *, rtx);
- 
- /* Initialize data in final at the beginning of a compilation.  */
- 
-@@ -1505,6 +1513,7 @@
-   int seen = 0;
- 
-   last_ignored_compare = 0;
-+  new_block = NEW_BLOCK_LABEL;
- 
- #ifdef SDB_DEBUGGING_INFO
-   /* When producing SDB debugging info, delete troublesome line number
-@@ -1571,6 +1580,7 @@
- 
-       insn = final_scan_insn (insn, file, optimize, prescan, 0, &seen);
-     }
-+  new_block = 0;
- }
- 
- const char *
-@@ -1851,6 +1861,7 @@
- #endif
-       if (prescan > 0)
- 	break;
-+      new_block = NEW_BLOCK_LABEL;
- 
-       if (LABEL_NAME (insn))
- 	(*debug_hooks->label) (insn);
-@@ -2009,6 +2020,26 @@
- 
- 	    break;
- 	  }
-+
-+#ifdef TARGET_IP28
-+	if (new_block)
-+	  {
-+	    /* .reorder: not really in the branch-delay-slot. */
-+	    if (! set_noreorder)
-+	      new_block = NEW_BLOCK_LABEL;
-+
-+	    if (new_block == NEW_BLOCK_BRANCH)
-+	      /* Not yet, only *after* the branch-delay-slot ! */
-+	      new_block = NEW_BLOCK_LABEL;
-+	    else
-+	      {
-+	        if (TARGET_IP28)
-+	          output_store_cache_barrier (file, insn);
-+	        new_block = 0;
-+	      }
-+	  }
-+#endif
-+
- 	/* Output this line note if it is the first or the last line
- 	   note in a row.  */
- 	if (notice_source_line (insn))
-@@ -2132,8 +2163,29 @@
- 	       clobbered by the function.  */
- 	    if (GET_CODE (XVECEXP (body, 0, 0)) == CALL_INSN)
- 	      {
-+#ifdef TARGET_IP28
-+	        if (TARGET_IP28)
-+	          new_block = NEW_BLOCK_LABEL;
-+#endif
- 		CC_STATUS_INIT;
- 	      }
-+#ifdef TARGET_IP28
-+	    /* Following a conditional branch sequence, we have a new basic
-+	       block.  */
-+	    if (TARGET_IP28)
-+	      {
-+		rtx insn = XVECEXP (body, 0, 0);
-+		rtx body = PATTERN (insn);
-+
-+		if ((GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == SET
-+		     && GET_CODE (SET_SRC (body)) != LABEL_REF)
-+		    || (GET_CODE (insn) == JUMP_INSN
-+			&& GET_CODE (body) == PARALLEL
-+			&& GET_CODE (XVECEXP (body, 0, 0)) == SET
-+			&& GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF))
-+		  new_block = NEW_BLOCK_LABEL;
-+	      }
-+#endif
- 	    break;
- 	  }
- 
-@@ -2188,6 +2240,20 @@
- 	  }
- #endif
- 
-+#ifdef TARGET_IP28
-+	/* Following a conditional branch, we have a new basic block.
-+	   But if we are inside a sequence, the new block starts after the
-+	   last insn of the sequence.  */
-+	if (TARGET_IP28 && final_sequence == 0
-+	    && (GET_CODE (insn) == CALL_INSN
-+	        || (GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == SET
-+	            && GET_CODE (SET_SRC (body)) != LABEL_REF)
-+	        || (GET_CODE (insn) == JUMP_INSN && GET_CODE (body) == PARALLEL
-+	            && GET_CODE (XVECEXP (body, 0, 0)) == SET
-+	            && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF)))
-+	      new_block = NEW_BLOCK_BRANCH;
-+#endif
-+
- #ifndef STACK_REGS
- 	/* Don't bother outputting obvious no-ops, even without -O.
- 	   This optimization is fast and doesn't interfere with debugging.
-@@ -2402,6 +2468,7 @@
- 
- 	    if (prev_nonnote_insn (insn) != last_ignored_compare)
- 	      abort ();
-+	    new_block = 0;
- 
- 	    /* We have already processed the notes between the setter and
- 	       the user.  Make sure we don't process them again, this is
-@@ -2435,6 +2502,7 @@
- 	    abort ();
- #endif
- 
-+	    new_block = 0;
- 	    return new;
- 	  }
- 
-@@ -3866,3 +3934,188 @@
-       symbol_queue_size = 0;
-     }
- }
-+
-+
-+#ifdef TARGET_IP28
-+
-+/* Check, whether `insn' is a possibly harmful store instruction, i.e.
-+   a store which might cause damage, if speculatively executed. */
-+
-+static int /*inline*/
-+check_pattern_for_store (rtx body)
-+{
-+  /* Check for (set (mem:M (non_stackpointer_address) ...)).  Here we
-+     assume, that addressing with the stackpointer accesses neither
-+     uncached-aliased nor invalid memory.  (May be, this applies to the
-+     global pointer and frame pointer also, but its saver not to assume
-+     it. And probably it's not worthwile to regard these registers) */
-+
-+  if (body && GET_CODE (body) == SET)
-+    {
-+      rtx xexp = SET_DEST (body);
-+      if (GET_CODE (xexp) == MEM)
-+        {
-+          /* Check for the most common stackpointer-addressing modes.
-+             It's not worthwile to avoid a cache barrier also on the
-+             remaining unfrequently used modes.  */
-+          xexp = XEXP (xexp, 0);
-+          switch (GET_CODE (xexp))
-+            {
-+            case REG:
-+              if (REGNO (xexp) == STACK_POINTER_REGNUM)
-+                return 0;
-+              break;
-+            case PLUS: case MINUS: /* always `SP + const' ? */
-+              if (GET_CODE (XEXP (xexp, 0)) == REG
-+                  && REGNO (XEXP (xexp, 0)) == STACK_POINTER_REGNUM)
-+                return 0;
-+              if (GET_CODE (XEXP (xexp, 1)) == REG
-+                  && REGNO (XEXP (xexp, 1)) == STACK_POINTER_REGNUM)
-+                return 0;
-+            }
-+          return 1;
-+        }
-+    }
-+  return 0;
-+}
-+
-+static int
-+check_insn_for_store (int state, rtx insn)
-+{
-+  /* Check for (ins (set (mem:M (dangerous_address)) ...)) or end of the
-+     current basic block.
-+     Criteria to recognize end-of/next basic-block are reduplicated here
-+     from final_scan_insn. */
-+
-+  rtx body;
-+  int code;
-+
-+  if (INSN_DELETED_P (insn))
-+    return 0;
-+
-+  switch (code = GET_CODE (insn))
-+    {
-+    case CODE_LABEL:
-+      return -1;
-+    case CALL_INSN:
-+    case JUMP_INSN:
-+    case INSN:
-+      body = PATTERN (insn);
-+      if (GET_CODE (body) == SEQUENCE)
-+        {
-+          /* A delayed-branch sequence */
-+          rtx ins0 = XVECEXP (body, 0, 0);
-+          rtx pat0 = PATTERN (ins0);
-+          int i;
-+          for (i = 0; i < XVECLEN (body, 0); i++)
-+            {
-+              rtx insq = XVECEXP (body, 0, i);
-+              if (! INSN_DELETED_P (insq))
-+                {
-+                  int j = check_insn_for_store (state|1, insq);
-+                  if (j)
-+                    return j;
-+                }
-+            }
-+          /* Following a conditional branch sequence, we have a new
-+             basic block.  */
-+          if (GET_CODE (ins0) == JUMP_INSN)
-+            if ((GET_CODE (pat0) == SET
-+                 && GET_CODE (SET_SRC (pat0)) != LABEL_REF)
-+                || (GET_CODE (pat0) == PARALLEL
-+                    && GET_CODE (XVECEXP (pat0, 0, 0)) == SET
-+                    && GET_CODE (SET_SRC (XVECEXP (pat0, 0, 0))) != LABEL_REF))
-+              return -1;
-+          /* Handle a call sequence like a conditional branch sequence */
-+          if (GET_CODE (ins0) == CALL_INSN)
-+            return -1;
-+          break;
-+        }
-+      if (GET_CODE (body) == PARALLEL)
-+        {
-+          int i;
-+          for (i = 0; i < XVECLEN (body, 0); i++)
-+            if (check_pattern_for_store (XVECEXP (body, 0, i)))
-+              return 1;
-+        }
-+      /* Now, only a `simple' INSN or JUMP_INSN remains to be checked. */
-+      if (code == INSN)
-+        if (check_pattern_for_store (body))
-+          return 1;
-+      /* Handle a CALL_INSN instruction like a conditional branch */
-+      if (code == JUMP_INSN || code == CALL_INSN)
-+        {
-+          /* Following a conditional branch, we have a new basic block. */
-+          int ckds = 0;
-+          if (code == CALL_INSN)
-+            ckds = 1;
-+          else
-+            {
-+              code = GET_CODE (body);
-+              if ((code == SET
-+                   && GET_CODE (SET_SRC (body)) != LABEL_REF)
-+                  || (code == PARALLEL
-+                      && GET_CODE (XVECEXP (body, 0, 0)) == SET
-+                      && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) != LABEL_REF))
-+                ckds = 1;
-+            }
-+          if (ckds)
-+            {
-+              /* But check insn(s) in delay-slot first.  If we could know in
-+                 advance that this jump is in `.reorder' mode, where gas will
-+                 insert a `nop' into the delay-slot, we could skip this test.
-+                 Since we don't know, always assume `.noreorder', sometimes
-+                 emitting a cache-barrier, that isn't needed.  */
-+              /* But if we are here recursively, already checking a (pseudo-)
-+                 delay-slot, we are done.  */
-+              if ( !(state & 2) )
-+                for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
-+                  switch (GET_CODE (insn))
-+                    {
-+                    case INSN:
-+                      if (check_insn_for_store (state|1|2, insn) > 0)
-+                        return 1;
-+                    case CODE_LABEL:
-+                    case CALL_INSN:
-+                    case JUMP_INSN:
-+                      return -1;
-+                    default:
-+                      /* skip NOTE,... */;
-+                    }
-+              return -1;
-+            }
-+        }
-+      /*break*/
-+    }
-+  return 0;
-+}
-+
-+/* Scan a basic block, starting with `insn', for a possibly harmful store
-+   instruction.  If found, output a cache barrier at the start of this
-+   block.  */
-+
-+static int
-+output_store_cache_barrier (FILE *file, rtx insn)
-+{
-+  for (; insn; insn = NEXT_INSN (insn))
-+    {
-+      int found = check_insn_for_store (0, insn);
-+      if (found < 0)
-+        break;
-+      if (found > 0)
-+        {
-+          /* found critical store instruction */
-+          ASM_OUTPUT_R10K_CACHE_BARRIER(file);
-+          return 1;
-+        }
-+    }
-+  fprintf(file, "\t%s Cache Barrier omitted.\n", ASM_COMMENT_START);
-+  return 0;
-+}
-+
-+#endif /* TARGET_IP28 */
-+
-+/*
-+ * final.c	Sun Jan 18 23:39:57 2004
-+ * final.c	Sat Sep 18 00:23:34 2004	ip28
-+ */
diff --git a/sys-devel/gcc-mips64/files/gcc-3.4.x-mips-add-march-r10k.patch b/sys-devel/gcc-mips64/files/gcc-3.4.x-mips-add-march-r10k.patch
deleted file mode 100644
index d02a5e91f1e7..000000000000
--- a/sys-devel/gcc-mips64/files/gcc-3.4.x-mips-add-march-r10k.patch
+++ /dev/null
@@ -1,460 +0,0 @@
-diff -Naurp gcc-3.4.1.orig/gcc/config/mips/mips.c gcc-3.4.1/gcc/config/mips/mips.c
---- gcc-3.4.1.orig/gcc/config/mips/mips.c	2004-06-28 09:58:42.000000000 -0400
-+++ gcc-3.4.1/gcc/config/mips/mips.c	2004-08-09 22:37:21.983939192 -0400
-@@ -707,6 +707,7 @@ const struct mips_cpu_info mips_cpu_info
- 
-   /* MIPS IV */
-   { "r8000", PROCESSOR_R8000, 4 },
-+  { "r10000", PROCESSOR_R10000, 4 },
-   { "vr5000", PROCESSOR_R5000, 4 },
-   { "vr5400", PROCESSOR_R5400, 4 },
-   { "vr5500", PROCESSOR_R5500, 4 },
-@@ -9401,6 +9402,9 @@ mips_issue_rate (void)
- {
-   switch (mips_tune)
-     {
-+    case PROCESSOR_R10000:
-+      return 4;
-+
-     case PROCESSOR_R5400:
-     case PROCESSOR_R5500:
-     case PROCESSOR_R7000:
-diff -Naurp gcc-3.4.1.orig/gcc/config/mips/mips.h gcc-3.4.1/gcc/config/mips/mips.h
---- gcc-3.4.1.orig/gcc/config/mips/mips.h	2004-03-11 16:52:33.000000000 -0500
-+++ gcc-3.4.1/gcc/config/mips/mips.h	2004-08-09 01:02:35.042149496 -0400
-@@ -66,6 +66,7 @@ enum processor_type {
-   PROCESSOR_R7000,
-   PROCESSOR_R8000,
-   PROCESSOR_R9000,
-+  PROCESSOR_R10000,
-   PROCESSOR_SB1,
-   PROCESSOR_SR71000
- };
-diff -Naurp gcc-3.4.1.orig/gcc/config/mips/mips.md gcc-3.4.1/gcc/config/mips/mips.md
---- gcc-3.4.1.orig/gcc/config/mips/mips.md	2004-06-25 03:35:30.000000000 -0400
-+++ gcc-3.4.1/gcc/config/mips/mips.md	2004-08-09 04:55:10.158649320 -0400
-@@ -103,6 +103,7 @@
- ;; arith	integer arithmetic instruction
- ;; darith	double precision integer arithmetic instructions
- ;; const	load constant
-+;; shift        integer shift
- ;; imul		integer multiply
- ;; imadd	integer multiply-add
- ;; idiv		integer divide
-@@ -120,7 +121,7 @@
- ;; multi	multiword sequence (or user asm statements)
- ;; nop		no operation
- (define_attr "type"
--  "unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
-+  "unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,shift,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
-   (cond [(eq_attr "jal" "!unset") (const_string "call")
- 	 (eq_attr "got" "load") (const_string "load")]
- 	(const_string "unknown")))
-@@ -214,7 +215,7 @@
- ;; Attribute describing the processor.  This attribute must match exactly
- ;; with the processor_type enumeration in mips.h.
- (define_attr "cpu"
--  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
-+  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sr71000"
-   (const (symbol_ref "mips_tune")))
- 
- ;; The type of hardware hazard associated with this instruction.
-@@ -305,12 +306,12 @@
- 
- (define_function_unit "memory" 1 0
-   (and (eq_attr "type" "load")
--       (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
-+       (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000,r10000"))
-   3 0)
- 
- (define_function_unit "memory" 1 0
-   (and (eq_attr "type" "load")
--       (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
-+       (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000,r10000"))
-   2 0)
- 
- (define_function_unit "memory"   1 0 (eq_attr "type" "store") 1 0)
-@@ -323,7 +324,7 @@
- 
- (define_function_unit "imuldiv"  1 0
-   (and (eq_attr "type" "imul,imadd")
--       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
-+       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000,r10000"))
-   17 17)
- 
- ;; On them mips16, we want to stronly discourage a mult from appearing
-@@ -375,7 +376,7 @@
- 
- (define_function_unit "imuldiv"  1 0
-   (and (eq_attr "type" "idiv")
--       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
-+       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000,r10000"))
-   38 38)
- 
- (define_function_unit "imuldiv"  1 0
-@@ -424,6 +425,40 @@
-        (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
-   68 68)
- 
-+;; R10000 has 2 integer ALUs
-+(define_function_unit "alu" 2 0
-+  (and (eq_attr "type" "arith,darith,shift")
-+       (eq_attr "cpu" "r10000"))
-+  1 0)
-+
-+;; Only ALU1 can do shifts.  We model shifts as an additional unit
-+(define_function_unit "alu1" 1 0
-+  (and (eq_attr "type" "shift")
-+       (eq_attr "cpu" "r10000"))
-+  1 0)
-+
-+;; only ALU2 does multiplications and divisions
-+(define_function_unit "alu2"  1 0
-+  (and (eq_attr "type" "imul")
-+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r10000")))
-+  6 6)
-+
-+(define_function_unit "alu2"  1 0
-+  (and (eq_attr "type" "imul")
-+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r10000")))
-+  10 10)
-+
-+(define_function_unit "alu2"  1 0
-+  (and (eq_attr "type" "idiv")
-+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r10000")))
-+  35 35)
-+
-+(define_function_unit "alu2"  1 0
-+  (and (eq_attr "type" "idiv")
-+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r10000")))
-+  67 67)
-+
-+
- ;; The R4300 does *NOT* have a separate Floating Point Unit, instead
- ;; the FP hardware is part of the normal ALU circuitry.  This means FP
- ;; instructions affect the pipe-line, and no functional unit
-@@ -432,11 +467,11 @@
- ;; instructions to be processed in the "imuldiv" unit.
- 
- (define_function_unit "adder" 1 1
--  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
-+  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r10000"))
-   3 0)
- 
- (define_function_unit "adder" 1 1
--  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
-+  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000,r10000"))
-   2 0)
- 
- (define_function_unit "adder" 1 1
-@@ -444,7 +479,7 @@
-   1 0)
- 
- (define_function_unit "adder" 1 1
--  (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
-+  (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r10000"))
-   4 0)
- 
- (define_function_unit "adder" 1 1
-@@ -456,6 +491,10 @@
-   3 0)
- 
- (define_function_unit "adder" 1 1
-+  (and (eq_attr "type" "fadd,fmadd") (eq_attr "cpu" "r10000"))
-+  2 0)
-+
-+(define_function_unit "adder" 1 1
-   (and (eq_attr "type" "fabs,fneg")
-        (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
-   2 0)
-@@ -467,7 +506,7 @@
- (define_function_unit "mult" 1 1
-   (and (eq_attr "type" "fmul")
-        (and (eq_attr "mode" "SF")
--	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
-+	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r10000")))
-   7 0)
- 
- (define_function_unit "mult" 1 1
-@@ -487,7 +526,7 @@
- 
- (define_function_unit "mult" 1 1
-   (and (eq_attr "type" "fmul")
--       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
-+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r10000")))
-   8 0)
- 
- (define_function_unit "mult" 1 1
-@@ -500,10 +539,14 @@
-        (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
-   6 0)
- 
-+(define_function_unit "mult" 1 1
-+  (and (eq_attr "type" "fmul,fmadd") (eq_attr "cpu" "r10000"))
-+  2 0)
-+
- (define_function_unit "divide" 1 1
-   (and (eq_attr "type" "fdiv")
-        (and (eq_attr "mode" "SF")
--	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
-+	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r10000")))
-   23 0)
- 
- (define_function_unit "divide" 1 1
-@@ -529,7 +572,7 @@
- (define_function_unit "divide" 1 1
-   (and (eq_attr "type" "fdiv")
-        (and (eq_attr "mode" "DF")
--	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
-+	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r10000")))
-   36 0)
- 
- (define_function_unit "divide" 1 1
-@@ -547,10 +590,21 @@
-        (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
-   61 0)
- 
-+;; divisions keep multiplier busy on R10000
-+(define_function_unit "mult" 1 1
-+  (and (eq_attr "type" "fdiv") 
-+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r10000")))
-+  12 14)
-+
-+(define_function_unit "mult" 1 1
-+  (and (eq_attr "type" "fdiv") 
-+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r10000")))
-+  19 21)
-+
- ;;; ??? Is this number right?
- (define_function_unit "divide" 1 1
-   (and (eq_attr "type" "fsqrt,frsqrt")
--       (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
-+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r10000")))
-   54 0)
- 
- (define_function_unit "divide" 1 1
-@@ -566,7 +620,7 @@
- ;;; ??? Is this number right?
- (define_function_unit "divide" 1 1
-   (and (eq_attr "type" "fsqrt,frsqrt")
--       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
-+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r10000")))
-   112 0)
- 
- (define_function_unit "divide" 1 1
-@@ -579,6 +633,17 @@
-        (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
-   36 0)
- 
-+;; sqrt is executed by multiplier on R10000
-+(define_function_unit "mult" 1 1
-+  (and (eq_attr "type" "fsqrt")
-+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r10000")))
-+  18 20)
-+
-+(define_function_unit "mult" 1 1
-+  (and (eq_attr "type" "fsqrt")
-+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r10000")))
-+  33 35)
-+
- ;; R4300 FP instruction classes treated as part of the "imuldiv"
- ;; functional unit:
- 
-@@ -3157,7 +3222,7 @@ dsrl\t%3,%3,1\n\
-   "@
-     sll\t%0,%1,0
-     sw\t%1,%0"
--  [(set_attr "type" "darith,store")
-+  [(set_attr "type" "shift,store")
-    (set_attr "mode" "SI")
-    (set_attr "extended_mips16" "yes,*")])
- 
-@@ -3191,7 +3256,7 @@ dsrl\t%3,%3,1\n\
-                                   (match_operand:DI 2 "small_int" "I"))))]
-   "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
-   "dsra\t%0,%1,%2"
--  [(set_attr "type" "darith")
-+  [(set_attr "type" "shift")
-    (set_attr "mode" "SI")])
- 
- (define_insn ""
-@@ -3200,7 +3265,7 @@ dsrl\t%3,%3,1\n\
-                                   (const_int 32))))]
-   "TARGET_64BIT && !TARGET_MIPS16"
-   "dsra\t%0,%1,32"
--  [(set_attr "type" "darith")
-+  [(set_attr "type" "shift")
-    (set_attr "mode" "SI")])
- 
- 
-@@ -5241,7 +5306,7 @@ dsrl\t%3,%3,1\n\
- 
-   return "sll\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"SI")])
- 
- (define_insn "ashlsi3_internal1_extend"
-@@ -5255,7 +5320,7 @@ dsrl\t%3,%3,1\n\
- 
-   return "sll\t%0,%1,%2";
- }
--  [(set_attr "type"    "arith")
-+  [(set_attr "type"    "shift")
-    (set_attr "mode"    "DI")])
- 
- 
-@@ -5273,7 +5338,7 @@ dsrl\t%3,%3,1\n\
- 
-   return "sll\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"SI")
-    (set_attr_alternative "length"
- 		[(const_int 4)
-@@ -5374,7 +5439,7 @@ sll\t%L0,%L1,%2\n\
-   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-   return "sll\t%M0,%L1,%2\;move\t%L0,%.";
- }
--  [(set_attr "type"	"darith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr "length"	"8")])
- 
-@@ -5429,7 +5494,7 @@ sll\t%L0,%L1,%2\n\
- 
-   return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
- }
--  [(set_attr "type"	"darith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr "length"	"16")])
- 
-@@ -5513,7 +5578,7 @@ sll\t%L0,%L1,%2\n\
- 
-   return "dsll\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")])
- 
- (define_insn ""
-@@ -5530,7 +5595,7 @@ sll\t%L0,%L1,%2\n\
- 
-   return "dsll\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr_alternative "length"
- 		[(const_int 4)
-@@ -5591,7 +5656,7 @@ sll\t%L0,%L1,%2\n\
- 
-   return "sra\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"SI")])
- 
- (define_insn "ashrsi3_internal2"
-@@ -5608,7 +5673,7 @@ sll\t%L0,%L1,%2\n\
- 
-   return "sra\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"SI")
-    (set_attr_alternative "length"
- 		[(const_int 4)
-@@ -5705,7 +5770,7 @@ sra\t%M0,%M1,%2\n\
-   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-   return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
- }
--  [(set_attr "type"	"darith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr "length"	"8")])
- 
-@@ -5760,7 +5825,7 @@ sra\t%M0,%M1,%2\n\
- 
-   return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
- }
--  [(set_attr "type"	"darith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr "length"	"16")])
- 
-@@ -5844,7 +5909,7 @@ sra\t%M0,%M1,%2\n\
- 
-   return "dsra\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")])
- 
- (define_insn ""
-@@ -5858,7 +5923,7 @@ sra\t%M0,%M1,%2\n\
- 
-   return "dsra\t%0,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr_alternative "length"
- 		[(const_int 4)
-@@ -5918,7 +5983,7 @@ sra\t%M0,%M1,%2\n\
- 
-   return "srl\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"SI")])
- 
- (define_insn "lshrsi3_internal2"
-@@ -5935,7 +6000,7 @@ sra\t%M0,%M1,%2\n\
- 
-   return "srl\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"SI")
-    (set_attr_alternative "length"
- 		[(const_int 4)
-@@ -6056,7 +6121,7 @@ srl\t%M0,%M1,%2\n\
-   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-   return "srl\t%L0,%M1,%2\;move\t%M0,%.";
- }
--  [(set_attr "type"	"darith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr "length"	"8")])
- 
-@@ -6111,7 +6176,7 @@ srl\t%M0,%M1,%2\n\
- 
-   return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
- }
--  [(set_attr "type"	"darith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr "length"	"16")])
- 
-@@ -6195,7 +6260,7 @@ srl\t%M0,%M1,%2\n\
- 
-   return "dsrl\t%0,%1,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")])
- 
- (define_insn ""
-@@ -6209,7 +6274,7 @@ srl\t%M0,%M1,%2\n\
- 
-   return "dsrl\t%0,%2";
- }
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"shift")
-    (set_attr "mode"	"DI")
-    (set_attr_alternative "length"
- 		[(const_int 4)
diff --git a/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild b/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild
deleted file mode 100644
index 8b9aac0e7182..000000000000
--- a/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild
+++ /dev/null
@@ -1,144 +0,0 @@
-# Copyright 1999-2006 Gentoo Foundation
-# Distributed under the terms of the GNU General Public License v2
-# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild,v 1.4 2006/08/17 16:08:47 kumba Exp $
-
-inherit eutils flag-o-matic
-
-# Variables 
-MYARCH="$(echo ${PN} | cut -d- -f2)"
-TMP_P="${P/-${MYARCH}/}"
-TMP_PN="${PN/-${MYARCH}/}"
-I="/usr"
-BRANCH_UPDATE=""
-
-DESCRIPTION="Mips64 Kernel Compiler"
-HOMEPAGE="http://www.gnu.org/software/gcc/gcc.html"
-
-SRC_URI="ftp://gcc.gnu.org/pub/gcc/releases/${TMP_P}/${TMP_P}.tar.bz2"
-#	mirror://gentoo/${TMP_P}-branch-update-${BRANCH_UPDATE}.patch.bz2"
-
-LICENSE="GPL-2 LGPL-2.1"
-SLOT="0"
-IUSE=""
-
-KEYWORDS="mips"
-
-DEPEND="virtual/libc
-	>=sys-devel/binutils-2.16.1
-	|| ( app-admin/eselect-compiler >=sys-devel/gcc-config-1.3.12-r4 )
-	!sys-devel/kgcc64"
-
-RDEPEND="virtual/libc
-	|| ( app-admin/eselect-compiler >=sys-devel/gcc-config-1.3.12-r4 )
-	>=sys-libs/zlib-1.1.4
-	>=sys-apps/texinfo-4.2-r4
-	!build? ( >=sys-libs/ncurses-5.2-r2 )"
-
-# Ripped from toolchain.eclass
-gcc_version_patch() {
-	[ -z "$1" ] && die "no arguments to gcc_version_patch"
-
-	sed -i -e 's~\(const char version_string\[\] = ".....\).*\(".*\)~\1 @GENTOO@\2~' ${S}/gcc/version.c || die "failed to add @GENTOO@"
-	sed -i -e "s:@GENTOO@:$1:g" ${S}/gcc/version.c || die "failed to patch version"
-	sed -i -e 's~http:\/\/gcc\.gnu\.org\/bugs\.html~http:\/\/bugs\.gentoo\.org\/~' ${S}/gcc/version.c || die "failed to update bugzilla URL"
-}
-
-pkg_setup() {
-	# glibc or uclibc?
-	if use elibc_glibc; then
-		MYUSERLAND="gnu"
-	elif use elibc_uclibc; then
-		MYUSERLAND="uclibc"
-	fi
-}
-
-src_unpack() {
-	unpack ${A}
-	cd ${WORKDIR}
-	ln -s ${TMP_P} ${P}
-	cd ${S}
-
-	# Patch in Branch update
-	if [ ! -z "${BRANCH_UPDATE}" ]; then
-		epatch ${WORKDIR}/${TMP_P}-branch-update-${BRANCH_UPDATE}.patch
-	fi
-
-	# Adds -march=r10000 support to gcc
-	epatch ${FILESDIR}/gcc-3.4.x-mips-add-march-r10k.patch
-
-	# Allows building of kernels for IP28 systems (enable w/ -mip28-cache-barrier)
-	epatch ${FILESDIR}/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch
-
-	# Make gcc's version info specific to Gentoo
-	gcc_version_patch "(Gentoo Linux ${PVR})"
-}
-
-src_compile() {
-	cd ${WORKDIR}
-	ln -s ${TMP_P} ${P}
-
-	append-flags "-Dinhibit_libc"
-
-	# Build in a separate build tree
-	mkdir -p ${WORKDIR}/build
-	cd ${WORKDIR}/build
-
-	einfo "Configuring GCC..."
-	if [ "`uname -m | grep 64`" ]; then
-		myconf="${myconf} --host=${MYARCH/64/}-unknown-linux-${MYUSERLAND}"
-	fi
-
-	addwrite "/dev/zero"
-	${S}/configure --prefix=${I} \
-		--disable-shared \
-		--disable-multilib \
-		--target=${MYARCH}-unknown-linux-${MYUSERLAND} \
-		--enable-languages=c \
-		--enable-threads=single \
-		${myconf} || die
-
-	einfo "Building GCC..."
-	S="${WORKDIR}/build" \
-	emake CFLAGS="${CFLAGS}" || die
-}
-
-src_install() {
-	# Do allow symlinks in ${I}/lib/gcc-lib/${CHOST}/${PV}/include as
-	# this can break the build.
-	for x in cd ${WORKDIR}/build/gcc/include/*
-	do
-		if [ -L ${x} ]
-		then
-			rm -f ${x}
-		fi
-	done
-
-	einfo "Installing GCC..."
-	# Do the 'make install' from the build directory
-	cd ${WORKDIR}/build
-	S="${WORKDIR}/build" \
-	make prefix=${D}${I} \
-		FAKE_ROOT="${D}" \
-		install || die
-
-	cd ${D}${I}/bin
-	ln -s ${MYARCH}-unknown-linux-${MYUSERLAND}-gcc gcc64
-	ln -s ${MYARCH}-unknown-linux-${MYUSERLAND}-gcc ${MYARCH}-linux-gcc
-}
-
-pkg_postinst() {
-	einfo ""
-	einfo "To facilitate an easier kernel build, you may wish to add the following line to your profile:"
-	einfo ""
-	einfo "For 2.4.x kernel builds:"
-	einfo "alias ${MYARCH}make=\"make ARCH=${MYARCH} CROSS_COMPILE=${MYARCH}-unknown-linux-${MYUSERLAND}-\""
-	einfo ""
-	einfo "For 2.6.x kernel builds:"
-	einfo "alias ${MYARCH}make=\"make ARCH=${MYARCH/64/} CROSS_COMPILE=${MYARCH}-unknown-linux-${MYUSERLAND}-\""
-	einfo ""
-	einfo "Then to compile a kernel, simply goto the kernel source directory, and issue:"
-	einfo "${MYARCH}make <target>"
-	einfo "Where <target> is one of the usual kernel targets"
-	einfo ""
-	epause 10
-}
diff --git a/sys-devel/gcc-mips64/metadata.xml b/sys-devel/gcc-mips64/metadata.xml
deleted file mode 100644
index 0adb8017442c..000000000000
--- a/sys-devel/gcc-mips64/metadata.xml
+++ /dev/null
@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
-<pkgmetadata>
-	<herd>mips</herd>
-	<maintainer>
-		<email>mips@gentoo.org</email>
-		<name>Mips Team</name>
-	</maintainer>
-
-	<longdescription>
-		gcc-mips64 is a package which will build a mips64 kernel compiler toolchain
-	</longdescription>
-</pkgmetadata>
-