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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-06-30 17:22:19 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-06-30 17:22:19 +0000
commitbf20dc076b30e474635679e167c3ac04b656bb63 (patch)
tree1674ae594e1150a81b6d54a553529b82b3144e5d /target-cris/translate.c
parentMove CPU save/load registration to common code. (diff)
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Spelling fixes, spotted by Stuart Brady.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4809 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/translate.c')
-rw-r--r--target-cris/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 2fc4101d4..81b61326f 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3141,7 +3141,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
num_insns++;
/* Check for delayed branches here. If we do it before
- actually genereating any host code, the simulator will just
+ actually generating any host code, the simulator will just
loop doing nothing for on this program location. */
if (dc->delayed_branch) {
dc->delayed_branch--;