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* Apply a similar libiberty fix as in 7d53105d for libopcodes and libgprofnggentoo/binutils-2.43-1Andreas K. Hüttel2024-08-052-4/+4
* Re-enable development on 2.43 branchNick Clifton2024-08-041-10/+10
* this-is-the-2.43-releasebinutils-2_43Nick Clifton2024-08-042-11/+11
* Updated translations for the bfd, binutils, gas, ld and opcodes directoriesNick Clifton2024-07-293-557/+573
* microMIPS: Add MT ASE instruction set supportYunQiang Su2024-07-262-1/+61
* Update version number to 2.42.90Nick Clifton2024-07-202-193/+195
* Add markers for 2.43 branch/releaseNick Clifton2024-07-201-0/+4
* MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki2024-07-191-2/+2
* MIPS/opcodes: Mark MT thread context move assembly idioms as aliasesMaciej W. Rozycki2024-07-191-38/+38
* MIPS/opcodes: Mark PAUSE as an aliasMaciej W. Rozycki2024-07-191-1/+1
* MIPS/opcodes: Reorder coprocessor moves alphabeticallyMaciej W. Rozycki2024-07-192-58/+62
* MIPS/opcodes: Make AL a shorthand for INSN2_ALIASMaciej W. Rozycki2024-07-192-56/+60
* MIPS/opcodes: Rename the AL membership shorthand to ALXMaciej W. Rozycki2024-07-191-88/+88
* MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su2024-07-191-2/+1
* MIPS/opcodes: Output thread context registers numerically with MFTR/MTTRMaciej W. Rozycki2024-07-191-2/+2
* MIPS/opcodes: Exclude $0 from "-x" R6 operand typeMaciej W. Rozycki2024-07-191-1/+1
* opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat2024-07-181-0/+19
* opcodes: aarch64: denote subclasses for insns of iclass dp_2srcIndu Bhagat2024-07-181-24/+24
* opcodes: aarch64: add flags to denote subclasses of uncond branchesIndu Bhagat2024-07-181-19/+19
* opcodes: aarch64: add flags to denote subclasses of arithmetic insnsIndu Bhagat2024-07-181-15/+15
* opcodes: aarch64: add flags to denote subclasses of ldst insnsIndu Bhagat2024-07-181-43/+43
* aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni2024-07-123-208/+330
* aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni2024-07-1210-283/+493
* aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni2024-07-124-210/+274
* aarch64: Add support for sve2p1 pmov instruction.srinath2024-07-086-221/+409
* aarch64: Add support for sve2p1 tbxq instruction.Srinath Parvathaneni2024-07-082-158/+170
* aarch64: Add support for sve2p1 zipq[1-2] instructions.Srinath Parvathaneni2024-07-082-160/+184
* aarch64: Add support for sve2p1 uzpq[1-2] instructions.Srinath Parvathaneni2024-07-082-151/+175
* aarch64: Add support for sve2p1 tblq instruction.Srinath Parvathaneni2024-07-082-175/+187
* aarch64: Add support for sve2p1 orqv instruction.Srinath Parvathaneni2024-07-082-152/+164
* aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)Matthieu Longo2024-07-051-0/+1
* aarch64: add STEP2 feature and its associated registersMatthieu Longo2024-07-051-0/+1
* aarch64: add SPMU2 feature and its associated registersMatthieu Longo2024-07-051-0/+1
* aarch64: add E3DSE feature and its associated registersMatthieu Longo2024-07-051-0/+2
* RISC-V: avoid use of match_opcode() in riscv_insn_types[]Jan Beulich2024-07-051-102/+102
* x86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili2024-07-052-2/+12
* Support APX CFCMOVCui, Lili2024-07-046-2237/+3269
* x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich2024-06-282-31/+34
* x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich2024-06-282-31/+31
* x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich2024-06-282-12/+12
* x86/APX: optimize certain {nf}-form insns to LEAJan Beulich2024-06-282-7/+7
* x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich2024-06-282-15/+15
* x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich2024-06-282-20/+20
* RISC-V: Add Zabha extension CAS instructions.Jiawei2024-06-281-0/+8
* aarch64: FP8 scale and convert - Implement minor improvementsVictor Do Nascimento2024-06-261-12/+12
* aarch64: Treat operand Rt_IN_SYS_ALIASES as register number (PR 31919)Jens Remus2024-06-251-1/+1
* aarch64: Fix FEAT_B16B16 sve2 instruction constraints.Srinath Parvathaneni2024-06-252-33/+33
* arch64: Fix the wrong constraint used for sve2p1 instructions.Srinath Parvathaneni2024-06-251-13/+12
* aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni2024-06-255-209/+206
* aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni2024-06-255-28/+24