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* x86: Turn PLT32 to PC32 only for PC-relative relocationsH.J. Lu2024-11-091-1/+10
* x86-64: Never make R_X86_64_GOT64 section relativeH.J. Lu2024-11-091-0/+1
* x86: correct .insn with opcode extension and VEX/XOP/EVEX encodingJan Beulich2024-08-201-1/+2
* x86: accept whitespace inside curly bracesJan Beulich2024-07-191-5/+18
* x86: undo '{' being a symbol-start characterJan Beulich2024-07-191-14/+98
* x86: split pseudo-prefix state from i386_insnJan Beulich2024-07-191-196/+197
* x86/APX: add CMPcc/CTESTcc cases to noreg64 testsJan Beulich2024-07-191-11/+29
* x86/APX: remove two inconsistenciesJan Beulich2024-07-121-18/+23
* x86/APX: correct TEST/CTESTcc with 1st operand being a memory oneJan Beulich2024-07-121-4/+8
* x86-64: Fix support for APX NF TLS IE with 2 operandsLingling Kong2024-07-051-3/+2
* gas: Enhance arch-specific SFrame configuration descriptionsJens Remus2024-07-041-0/+5
* x86: Remove unused SFrame CFI RA register variableJens Remus2024-07-041-1/+0
* Support APX CFCMOVCui, Lili2024-07-041-1/+1
* x86-64: Support APX NF TLS IE with 2 operandsLingling Kong2024-07-031-2/+8
* x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich2024-06-281-1/+16
* x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich2024-06-281-2/+8
* x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich2024-06-281-0/+70
* x86-64: restrict by-imm31 optimizationJan Beulich2024-06-281-12/+15
* x86/APX: optimize certain {nf}-form insns to LEAJan Beulich2024-06-281-8/+236
* x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich2024-06-281-1/+21
* x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich2024-06-281-1/+83
* x86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich2024-06-211-0/+38
* x86: optimize left-shift-by-1Jan Beulich2024-06-211-0/+79
* x86: %riz, %rip, and %eip don't require REXJan Beulich2024-06-211-2/+2
* x86: don't suppress errors when optimizingJan Beulich2024-06-211-1/+16
* Support APX CCMP and CTESTCui, Lili2024-06-181-1/+145
* x86/APX: convert ZU to operand constraintJan Beulich2024-06-101-1/+5
* x86: reduce check_{byte,word,long,qword}_reg() overheadJan Beulich2024-05-311-4/+15
* x86/Intel: warn about undue mnemonic suffixesJan Beulich2024-05-291-0/+13
* x86/Intel: SHLD/SHRD have dual meaningJan Beulich2024-05-291-2/+5
* x86: simplify VexVVVV_SRC2 handling for the XOP caseJan Beulich2024-05-241-9/+5
* x86: simplify / consolidate check_{word,long,qword}_reg()Jan Beulich2024-05-241-16/+4
* x86: correct VCVT{,U}SI2SDJan Beulich2024-05-241-5/+47
* Support APX zero-upperCui, Lili2024-05-221-2/+3
* X86: Remove "i.rex" to eliminate extra conditional branchCui, Lili2024-05-221-1/+1
* Add check for 8-bit old registers in EVEX formatCui, Lili2024-05-221-3/+4
* x86: Split REX/REX2 old registers judgment.Cui, Lili2024-05-221-16/+14
* x86: Drop using extension_opcode to encode vvvv registerCui, Lili2024-05-061-6/+3
* x86: Drop SwapSourcesCui, Lili2024-05-061-8/+11
* x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili2024-05-061-15/+17
* x86/APX: extend SSE2AVX coverageJan Beulich2024-05-031-2/+7
* x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili2024-04-221-1/+4
* x86: Fix a memory leak in md_assembleH.J. Lu2024-04-161-5/+8
* x86-64: Use long NOPs for Intel Core processorsH.J. Lu2024-04-101-5/+35
* Support APX NFCui, Lili2024-04-071-4/+31
* x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili2024-04-031-7/+0
* x86/SSE2AVX: move checkingJan Beulich2024-03-281-11/+10
* x86/SSE2AVX: respect prefixesJan Beulich2024-03-281-2/+3
* x86: fix Solaris testsuite failuresJan Beulich2024-03-221-6/+3
* x86/APX: legacy promoted insns can't access %xmm16-%xmm31Jan Beulich2024-03-151-0/+7